Texas Instruments: 2023 Analog Campus Account

The source and its scope

The source is an October 2024 Medium article published by the IIT Kharagpur Student Welfare Group. It records an interview with Arpan Deb, who says he received an Analog Engineer offer through 2023 campus placements. The article is specific to his institute, selected profiles, projects, and interview. It cannot establish a current company-wide process.

The account says the assessment was organised into Analog, Digital, and Embedded Software profiles, and that a student could appear for one or at most two. Arpan selected Analog and Digital. That supports separate preparation for the chosen domains in this drive, but it does not prove that the same profile menu or limit applies now.

Question counts, negative marking, the author's clearing estimate, interview timing, and offer timing are candidate-reported for that cycle. Before preparing, compare the live campus notice or job listing with this account and discard any historical detail that conflicts.

The source gives unusually specific Analog-profile evidence: first-order and second-order RC circuits, poles and zeros, current mirrors, SAR ADC sampling-capacitance calculations, and benefits of gray encoding in flash ADCs. It later describes detailed questions on Arpan's ADC projects. That makes the account useful without requiring a general claim about every Texas Instruments interview.

Online assessment breakdown: aptitude plus profile-specific technical

In the reported drive, the online assessment had a common aptitude section plus a technical section for each profile selected by the candidate. Here is the structure Arpan describes in the FORESIGHT writeup:

Arpan says the common aptitude section had 14 to 15 questions, a stated time limit, and negative marking. He gives 11 to 12 correct answers as his view of what was enough to clear the section. That is not presented as an official published cutoff. The named topics were time and work, speed and time, linear equations, permutations and combinations, probability, and basic number theory.

The technical section differs sharply by profile:

The article provides detailed topic lists for the Analog and Digital sections Arpan selected. It does not provide a corresponding Embedded Software topic list. This guide therefore does not manufacture one. Candidates considering Embedded Software should use the current notice and role description rather than extrapolating from the Analog and Digital evidence.

The interview: technical problems, then project depth

Arpan reports that the Analog interview began with about 20 to 30 minutes of technical problems. These included RC circuits, poles and zeros, current mirroring, SAR ADC sampling capacitance, and gray encoding in flash ADCs. He says the next 30 to 40 minutes focused on his resume and ADC projects.

For project preparation, distinguish facts stated in the source from invented sample questions. The source says the interviewer asked about power consumption, comparator topology, the ADC algorithm, and a redundancy algorithm from a paper. A candidate should be ready to justify every resume item, but this article does not attribute an unreported compensation-strategy question to Texas Instruments.

The order matters because the original draft had reversed it. In this account, subject questions came first and the resume discussion followed. Another interviewer could choose a different order, so the durable preparation lesson is to understand both the domain fundamentals and every project claim.

Arpan says he was offered the Analog Engineer role within about 15 to 20 minutes, before his Digital-profile interview. The source does not explain the internal decision or establish a typical communication time. Treat it only as his reported sequence.

The account does not state an official CGPA minimum or compensation figure. It mentions a possible interview preference based on scores and CGPA, but Arpan explicitly labels that as an observation that may not hold. This guide does not turn it into a rule or add a salary comparison.

Preparation derived from the reported evidence

Use the current notice to choose the role and profile. Then use the source's detailed Analog and Digital topics as historical practice evidence where they remain relevant.

Choose only from the current options. The 2023 account allowed up to two profiles, but a current drive may differ. Select a profile whose fundamentals and projects you can defend rather than relying on an unsupported claim that one pairing is universally smarter.

Practise the reported aptitude topics. Work from the actual marking rules in the current notice. The historical account names arithmetic, speed and time, linear equations, permutations and combinations, probability, and basic number theory. Do not convert the author's estimate into a calculated cutoff percentage.

Make each project claim auditable. Explain the problem, your contribution, circuit or architecture, design choices, calculations, verification method, observed result, limitations, and connection to any cited paper. Remove metrics and ownership claims you cannot support.

Profile-specific technical review. Use the Analog and Digital topics above as a historical practice map only where the current role overlaps. Work through each selected concept from definitions to a derivation, schematic, timing argument, or small implementation as appropriate. The source provides no Embedded Software topic list, so this guide cannot prescribe one.

Seek a technical review. Ask someone qualified in the domain to challenge the assumptions, derivations, and evidence behind your project. The goal is to expose gaps, not to imitate an unverified company script.

For placement cells: Label this as a 2023 IIT Kharagpur account and pair it with the current campus notice. Historical detail is useful only when its date and scope remain visible.

Common mistakes and red flags

• Bluffing on project depth. Arpan reports detailed questions on his ADC work. List only contributions and results you can defend.
• Calling an estimate an official cutoff. The 11 to 12 answer figure is the interviewee's advice, not a published rule.
• Inventing an Embedded syllabus. The cited account gives detailed Analog and Digital lists but not an Embedded list.
• Expecting the reported offer timing. One candidate's 15 to 20 minute sequence is not a baseline.
• Trusting an unverified CTC number. No compensation figure was disclosed in the FORESIGHT writeup, so this source cannot validate one. Use the current written role notice or offer.

Real-world data points

• 3 parallel fresher profiles: Analog Design, Digital Design, Embedded Software (candidate-reported, FORESIGHT 2024 cycle, IIT Kharagpur)
• Up to 2 profiles per candidate allowed in registration (candidate-reported, FORESIGHT 2024 writeup)
• 14 to 15 aptitude questions with negative marking, common across all profiles (candidate-reported)
• Approximately 11 to 12 correct answers was Arpan's clearing estimate, not an official cutoff
• First 20 to 30 minutes of the reported interview covered Analog technical problems, followed by about 30 to 40 minutes on the resume and ADC projects
• 15 to 20 minutes from interview end to offer communication for one Analog-profile candidate (candidate-reported, outlier scenario)
• Aptitude topics: arithmetic, speed and time, linear equations, permutations and combinations, probability, number theory (candidate-reported)
• Source publication: IIT Kharagpur Student Welfare Group, October 2024, discussing Arpan Deb's 2023 offer

Sources & credits

• https://medium.com/@swgiitkgp/foresight-2024-placement-at-texas-instruments-arpan-deb-8862e71a40c4