Qualcomm Interview Questions 2026 - Embedded, DSP & VLSI Focus

Qualcomm Overview

Attribute	Details
Founded	1985
Headquarters	San Diego, CA (India: Bangalore, Hyderabad, Chennai)
Employees in India	15,000+
Core Business	Wireless Technology, Semiconductors, 5G
Key Products	Snapdragon Processors, 5G Modems, RF Front-End
R&D Focus	Mobile SoC, AI/ML on-device, Automotive

Qualcomm is the world's largest fabless semiconductor company and a leader in wireless technology innovation. Their India R&D centers work on cutting-edge chip design, software, and system integration.

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Qualcomm Interview Process 2026

Hiring for Roles

Role	Focus Areas	Package Range
ASIC Design Engineer	VLSI, Verilog, STA	₹12-20 LPA
Embedded Software Engineer	C/C++, RTOS, Drivers	₹10-18 LPA
DSP Engineer	Signal processing, MATLAB	₹12-20 LPA
System Validation	Testing, Python, Automation	₹10-16 LPA
Hardware Engineer	PCB, RF, Power management	₹10-16 LPA

Selection Stages

Stage	Duration	Format
Online Test	90 mins	Aptitude + Technical MCQs + Coding
Technical Round 1	60-90 mins	Core CS/EE concepts
Technical Round 2	60-90 mins	Domain-specific deep dive
Technical Round 3	45-60 mins	Design/Architecture
Managerial Round	30-45 mins	Project discussion
HR Interview	20-30 mins	Behavioral, Compensation

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Embedded Systems Questions

Question 1: Explain Interrupt Handling in ARM

/* ARM Cortex-M Interrupt Handling */

/* Vector Table Structure */
/* 0x0000_0000: Initial SP value */
/* 0x0000_0004: Reset handler */
/* 0x0000_0008: NMI handler */
/* 0x0000_000C: HardFault handler */
/* ... */

/* NVIC (Nested Vectored Interrupt Controller) */
#define NVIC_ISER0      (*(volatile uint32_t *)0xE000E100)
#define NVIC_ICER0      (*(volatile uint32_t *)0xE000E180)
#define NVIC_ISPR0      (*(volatile uint32_t *)0xE000E200)
#define NVIC_IPR0       (*(volatile uint32_t *)0xE000E400)

/* Enable Interrupt */
void enable_interrupt(uint8_t irq_num) {
    NVIC_ISER0 = (1 << irq_num);
}

/* Set Priority (0-255, lower is higher priority) */
void set_priority(uint8_t irq_num, uint8_t priority) {
    uint32_t reg_num = irq_num / 4;
    uint32_t byte_offset = (irq_num % 4) * 8;
    
    volatile uint32_t *reg = &NVIC_IPR0 + reg_num;
    *reg = (*reg & ~(0xFF << byte_offset)) | 
           (priority << byte_offset);
}

/* Interrupt Service Routine */
void __attribute__((interrupt)) TIM2_IRQHandler(void) {
    // Clear interrupt flag
    TIM2->SR &= ~TIM_SR_UIF;
    
    // Handle interrupt
    g_tick_count++;
}

Question 2: Memory-Mapped I/O vs Port-Mapped I/O

Feature	Memory-Mapped I/O (MMIO)	Port-Mapped I/O (PMIO)
Address Space	Shares memory space	Separate I/O space
Instructions	Standard load/store	Special IN/OUT instructions
Address Range	Large (32/64-bit)	Limited (0-65535)
Protection	MMU can protect	Special I/O privilege level
Performance	Cacheable (with care)	Always uncached
Examples	ARM, RISC-V, MIPS	x86 (legacy)

/* Memory-Mapped I/O Example (ARM) */
#define GPIOA_BASE      0x40020000
#define GPIOA_MODER     (*(volatile uint32_t *)(GPIOA_BASE + 0x00))
#define GPIOA_ODR       (*(volatile uint32_t *)(GPIOA_BASE + 0x14))

void gpio_set_pin(uint8_t pin) {
    GPIOA_ODR |= (1 << pin);  // Regular memory write
}

/* Port-Mapped I/O Example (x86) */
void outb(uint16_t port, uint8_t val) {
    __asm__ __volatile__("outb %0, %1" : : "a"(val), "Nd"(port));
}

uint8_t inb(uint16_t port) {
    uint8_t ret;
    __asm__ __volatile__("inb %1, %0" : "=a"(ret) : "Nd"(port));
    return ret;
}

Question 3: volatile Keyword in C/C++

/* volatile prevents compiler optimization for memory accesses */

/* Without volatile - compiler might optimize away reads */
int sensor_value;
void wait_for_sensor() {
    while (sensor_value == 0) {
        // Compiler may think this never changes!
    }
}

/* With volatile - tells compiler value can change externally */
volatile int sensor_value;
void wait_for_sensor() {
    while (sensor_value == 0) {
        // Compiler will read from memory each time
    }
}

/* Common use cases for volatile: */
// 1. Hardware registers
volatile uint32_t *timer_reg = (volatile uint32_t *)0x40000000;

// 2. Variables modified by ISR
volatile uint32_t interrupt_count = 0;
void ISR_Handler(void) {
    interrupt_count++;  // Modified by interrupt
}

// 3. Shared variables in multi-threaded (with proper synchronization)
volatile int shared_data;

// 4. Memory-mapped peripherals
#define UART_DR (*(volatile uint8_t *)0x101F1000)

Question 4: Bootloader Design

/* Simple Bootloader Structure */

/* Memory Layout:
 * 0x0000_0000 - 0x0000_FFFF: Bootloader (64KB)
 * 0x0001_0000 - 0x07FF_FFFF: Application
 * 0x0800_0000+: Other regions
 */

#define BOOTLOADER_START    0x00000000
#define APP_START_ADDR      0x00010000
#define APP_VECTOR_TABLE    APP_START_ADDR

/* Bootloader State Machine */
typedef enum {
    BOOT_STATE_INIT,
    BOOT_STATE_CHECK_UPDATE,
    BOOT_STATE_LOAD_APP,
    BOOT_STATE_JUMP_APP,
    BOOT_STATE_RECOVERY
} BootState;

/* Jump to Application */
void jump_to_application(uint32_t addr) {
    // Get application vector table
    uint32_t *app_vector_table = (uint32_t *)addr;
    
    // Get stack pointer and reset handler
    uint32_t stack_ptr = app_vector_table[0];
    uint32_t reset_handler = app_vector_table[1];
    
    // Disable interrupts
    __disable_irq();
    
    // Set vector table offset
    SCB->VTOR = addr;
    
    // Set stack pointer
    __set_MSP(stack_ptr);
    
    // Jump to application
    typedef void (*app_entry_t)(void);
    app_entry_t app_entry = (app_entry_t)reset_handler;
    app_entry();
}

/* Firmware Update via UART */
bool update_firmware(void) {
    uint8_t buffer[1024];
    uint32_t write_addr = APP_START_ADDR;
    
    while (1) {
        // Receive data packet
        int len = uart_receive(buffer, sizeof(buffer), 5000);
        if (len <= 0) break;
        
        // Verify packet
        if (!verify_packet(buffer, len)) {
            return false;
        }
        
        // Write to flash
        flash_write(write_addr, buffer, len);
        write_addr += len;
        
        // Check for completion marker
        if (is_last_packet(buffer)) {
            break;
        }
    }
    
    // Verify complete image
    return verify_firmware_image(APP_START_ADDR);
}

Question 5: DMA (Direct Memory Access)

/* DMA Controller Programming */

/* DMA Configuration Structure */
typedef struct {
    uint32_t source_addr;
    uint32_t dest_addr;
    uint32_t buffer_size;
    uint8_t  source_inc;
    uint8_t  dest_inc;
    uint8_t  data_size;     // 8, 16, or 32 bit
    uint8_t  mode;          // Normal or Circular
    uint8_t  priority;
} DMA_Config_t;

/* Initialize DMA for Memory-to-Peripheral transfer (UART TX) */
void dma_init_uart_tx(DMA_Config_t *config) {
    // Enable DMA clock
    RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
    
    // Disable channel before configuration
    DMA2_Stream7->CR &= ~DMA_SxCR_EN;
    while (DMA2_Stream7->CR & DMA_SxCR_EN);  // Wait
    
    // Configure addresses
    DMA2_Stream7->PAR = config->dest_addr;   // UART DR
    DMA2_Stream7->M0AR = config->source_addr;
    DMA2_Stream7->NDTR = config->buffer_size;
    
    // Configure control register
    uint32_t cr = 0;
    cr |= DMA_SxCR_CHSEL_2;                  // Channel 4 for UART1 TX
    cr |= DMA_SxCR_PL_1;                     // High priority
    cr |= DMA_SxCR_MSIZE_0;                  // 8-bit memory
    cr |= DMA_SxCR_PSIZE_0;                  // 8-bit peripheral
    cr |= DMA_SxCR_MINC;                     // Memory increment
    cr |= DMA_SxCR_DIR_1;                    // Memory to peripheral
    cr |= DMA_SxCR_TCIE;                     // Transfer complete interrupt
    
    DMA2_Stream7->CR = cr;
    
    // Enable DMA interrupt in NVIC
    NVIC_EnableIRQ(DMA2_Stream7_IRQn);
}

void dma_start_transfer(void) {
    DMA2_Stream7->CR |= DMA_SxCR_EN;
}

void DMA2_Stream7_IRQHandler(void) {
    if (DMA2->HISR & DMA_HISR_TCIF7) {
        DMA2->HIFCR = DMA_HIFCR_CTCIF7;      // Clear flag
        // Transfer complete callback
        uart_tx_complete_callback();
    }
}

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DSP (Digital Signal Processing) Questions

Question 6: FFT Implementation

#include <complex.h>
#include <math.h>

/* Cooley-Tukey FFT Algorithm */

#define PI 3.14159265358979323846

/* Bit reversal permutation */
void bit_reverse(complex double *data, int n) {
    int j = 0;
    for (int i = 0; i < n - 1; i++) {
        if (i < j) {
            complex double temp = data[i];
            data[i] = data[j];
            data[j] = temp;
        }
        
        int k = n >> 1;
        while (k <= j) {
            j -= k;
            k >>= 1;
        }
        j += k;
    }
}

/* Iterative FFT */
void fft(complex double *data, int n) {
    bit_reverse(data, n);
    
    for (int step = 2; step <= n; step <<= 1) {
        double angle = -2.0 * PI / step;
        complex double w_step = cos(angle) + I * sin(angle);
        
        for (int group = 0; group < n; group += step) {
            complex double w = 1.0;
            
            for (int pair = 0; pair < step / 2; pair++) {
                complex double u = data[group + pair];
                complex double v = w * data[group + pair + step / 2];
                
                data[group + pair] = u + v;
                data[group + pair + step / 2] = u - v;
                
                w *= w_step;
            }
        }
    }
}

/* Fixed-point FFT (16-bit) for embedded */
#define Q15_SHIFT 15

typedef struct {
    int16_t real;
    int16_t imag;
} Complex_Q15;

/* Fixed-point multiplication */
int16_t q15_mult(int16_t a, int16_t b) {
    return (int16_t)(((int32_t)a * (int32_t)b) >> Q15_SHIFT);
}

Question 7: FIR Filter Design

/* Finite Impulse Response Filter */

/* Direct Form FIR Implementation */
#define FIR_TAPS 64

typedef struct {
    int16_t coeffs[FIR_TAPS];
    int16_t delay_line[FIR_TAPS];
    uint8_t curr_index;
} FIR_Filter;

/* Initialize FIR filter with coefficients */
void fir_init(FIR_Filter *filt, const int16_t *coeffs) {
    memcpy(filt->coeffs, coeffs, FIR_TAPS * sizeof(int16_t));
    memset(filt->delay_line, 0, FIR_TAPS * sizeof(int16_t));
    filt->curr_index = 0;
}

/* Process single sample */
int16_t fir_process(FIR_Filter *filt, int16_t input) {
    int32_t acc = 0;
    uint8_t tap = filt->curr_index;
    
    // Insert new sample
    filt->delay_line[tap] = input;
    
    // Compute convolution
    for (uint8_t i = 0; i < FIR_TAPS; i++) {
        acc += (int32_t)filt->coeffs[i] * filt->delay_line[tap];
        tap = (tap == 0) ? (FIR_TAPS - 1) : (tap - 1);
    }
    
    // Update index
    filt->curr_index = (filt->curr_index + 1) % FIR_TAPS;
    
    // Return scaled result
    return (int16_t)(acc >> 15);
}

/* Optimized version using circular buffer */
int16_t fir_process_optimized(FIR_Filter *filt, int16_t input) {
    int32_t acc = 0;
    
    // Insert sample and update pointer
    filt->delay_line[filt->curr_index] = input;
    
    uint8_t index = filt->curr_index;
    for (uint8_t i = 0; i < FIR_TAPS; i++) {
        acc += (int32_t)filt->coeffs[i] * filt->delay_line[index];
        index = (index == 0) ? (FIR_TAPS - 1) : (index - 1);
    }
    
    filt->curr_index = (filt->curr_index + 1) % FIR_TAPS;
    return (int16_t)(acc >> 15);
}

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VLSI & ASIC Design Questions

Question 8: Verilog Coding Examples

// 8-bit Counter with synchronous reset
module counter_8bit (
    input wire clk,
    input wire rst_n,
    input wire enable,
    output reg [7:0] count
);

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            count <= 8'b0;
        end else if (enable) begin
            count <= count + 1'b1;
        end
    end

endmodule

// Synchronous FIFO
module sync_fifo #(
    parameter DEPTH = 16,
    parameter WIDTH = 32
)(
    input wire clk,
    input wire rst_n,
    input wire wr_en,
    input wire rd_en,
    input wire [WIDTH-1:0] wr_data,
    output reg [WIDTH-1:0] rd_data,
    output wire full,
    output wire empty
);

    reg [WIDTH-1:0] mem [0:DEPTH-1];
    reg [$clog2(DEPTH):0] wr_ptr, rd_ptr;
    
    assign full = (wr_ptr[$clog2(DEPTH)] != rd_ptr[$clog2(DEPTH)]) && 
                  (wr_ptr[$clog2(DEPTH)-1:0] == rd_ptr[$clog2(DEPTH)-1:0]);
    assign empty = (wr_ptr == rd_ptr);
    
    always @(posedge clk) begin
        if (wr_en && !full) begin
            mem[wr_ptr[$clog2(DEPTH)-1:0]] <= wr_data;
            wr_ptr <= wr_ptr + 1'b1;
        end
    end
    
    always @(posedge clk) begin
        if (rd_en && !empty) begin
            rd_data <= mem[rd_ptr[$clog2(DEPTH)-1:0]];
            rd_ptr <= rd_ptr + 1'b1;
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wr_ptr <= 'b0;
            rd_ptr <= 'b0;
        end
    end

endmodule

// Pipelined Multiplier (4-stage)
module pipelined_multiplier (
    input wire clk,
    input wire [15:0] a,
    input wire [15:0] b,
    output reg [31:0] product
);

    reg [15:0] a_reg [0:3];
    reg [15:0] b_reg [0:3];
    reg [31:0] partial [0:3];
    
    always @(posedge clk) begin
        // Stage 1: Input registration
        a_reg[0] <= a;
        b_reg[0] <= b;
        
        // Stage 2-4: Pipeline stages
        a_reg[1] <= a_reg[0];
        b_reg[1] <= b_reg[0];
        a_reg[2] <= a_reg[1];
        b_reg[2] <= b_reg[1];
        a_reg[3] <= a_reg[2];
        b_reg[3] <= b_reg[2];
        
        // Stage 4: Multiplication
        partial[3] <= a_reg[3] * b_reg[3];
        
        // Output
        product <= partial[3];
    end

endmodule

Question 9: Static Timing Analysis (STA) Basics

# TCL script for STA (simplified)

# Read design files
read_verilog design.v
read_liberty stdcell.lib

# Link design
link_design top

# Read constraints
read_sdc constraints.sdc

# Report timing
report_timing -delay_type max -path_count 10
report_timing -delay_type min -path_count 10

# Check violations
set violations [check_timing]

# Setup time check formula:
# T_launch + T_ck2q + T_comb < T_capture + T_cycle - T_setup
#
# Hold time check formula:
# T_launch + T_ck2q + T_comb > T_capture + T_hold

Key STA Concepts:

Concept	Description
Setup Time	Data must be stable before clock edge
Hold Time	Data must remain stable after clock edge
Slack	Difference between required and actual time
Critical Path	Longest path determining max frequency
Clock Skew	Difference in clock arrival times
Clock Jitter	Variation in clock period
Metastability	Unstable state in synchronizers

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C Programming Questions

Question 10: Bit Manipulation

/* Essential Bit Manipulation Operations */

/* Check if bit is set */
#define IS_BIT_SET(val, pos) (((val) >> (pos)) & 1)

/* Set a bit */
#define SET_BIT(val, pos) ((val) | (1 << (pos)))

/* Clear a bit */
#define CLEAR_BIT(val, pos) ((val) & ~(1 << (pos)))

/* Toggle a bit */
#define TOGGLE_BIT(val, pos) ((val) ^ (1 << (pos)))

/* Count set bits (Brian Kernighan's algorithm) */
int count_set_bits(uint32_t n) {
    int count = 0;
    while (n) {
        n &= (n - 1);  // Clear least significant set bit
        count++;
    }
    return count;
}

/* Reverse bits in a byte */
uint8_t reverse_bits(uint8_t b) {
    b = (b & 0xF0) >> 4 | (b & 0x0F) << 4;
    b = (b & 0xCC) >> 2 | (b & 0x33) << 2;
    b = (b & 0xAA) >> 1 | (b & 0x55) << 1;
    return b;
}

/* Find position of only set bit */
int find_only_set_bit(uint32_t n) {
    if (n && !(n & (n - 1))) {  // Check if power of 2
        int pos = 0;
        while (n >>= 1) pos++;
        return pos;
    }
    return -1;  // Not a power of 2
}

/* Swap without temporary variable */
void swap(int *a, int *b) {
    *a = *a ^ *b;
    *b = *a ^ *b;
    *a = *a ^ *b;
}

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HR Interview Questions

Q1: Why Qualcomm?

Sample Answer: "Qualcomm is at the forefront of wireless innovation. My interest in embedded systems and signal processing aligns perfectly with Qualcomm's work in 5G and mobile SoCs. I'm excited about the opportunity to contribute to products that billions of people use daily. The technical depth and focus on R&D at Qualcomm make it the ideal place to grow as a hardware-software engineer."

Q2: Describe a hardware-software co-design challenge you faced

STAR Format:

• Situation: UART driver dropping data at high baud rates
• Task: Fix without hardware changes
• Action: Implemented DMA, optimized buffer sizes, reduced interrupt latency
• Result: Achieved reliable 2 Mbps communication, 10x improvement

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5 Frequently Asked Questions (FAQs)

Q1: What is the salary for freshers at Qualcomm in 2026?

A: Qualcomm offers ₹10-20 LPA for freshers, depending on the role and location.

Q2: Does Qualcomm hire CS students or only ECE?

A: Qualcomm hires both CS and ECE students. CS students are preferred for software/embedded roles, ECE for hardware/VLSI.

Q3: What programming languages should I know?

A: C/C++ is essential. Python for scripting/validation. Verilog/VHDL for VLSI roles.

Q4: Is knowledge of ARM architecture required?

A: Basic ARM architecture knowledge is expected for embedded roles. Deep knowledge is a plus.

Q5: How competitive is Qualcomm placement?

A: Qualcomm is highly selective with 5-10% selection rate. Strong fundamentals in C, OS, and hardware are crucial.

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Last Updated: March 2026 Source: Qualcomm Careers, Interview Experiences, Glassdoor